Technical Document
Specifications
Maximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Country of Origin
Taiwan, Province Of China
Product details
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.
₹ 3,400.01
₹ 3,400.01 Each (Supplied in a Tray) (Exc. GST)
₹ 4,012.01
₹ 4,012.012 Each (Supplied in a Tray) (inc. GST)
Production pack (Tray)
1
RS Components & Controls (I) Ltd
Distribution hub - B-89, Sector 67, Noida, Gautam Budh Nagar, (Uttar Pradesh), 201 301
₹ 3,400.01
₹ 3,400.01 Each (Supplied in a Tray) (Exc. GST)
₹ 4,012.01
₹ 4,012.012 Each (Supplied in a Tray) (inc. GST)
Production pack (Tray)
1
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Technical Document
Specifications
Maximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Country of Origin
Taiwan, Province Of China
Product details
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.